1. Field of the Invention
The present invention relates to a clock skew estimation mechanism, and more particularly, to a method and estimation apparatus for estimating the clock skew between two clocks.
2. Description of the Prior Art
Process variations greatly impact yield rate in semiconductor processes when advanced to the deep sub-micron stage. The process variation not only affects the transmitting time of the data signal, but also the clock skew variation of the clock in the chip during a worst case scenario. Based on the fact that the synchronization circuit synchronizes the data according to the clock of the chip, the work timing of the circuit will be affected seriously if the clock of chip shifts forward and backward because of the process variation. The conventional solution is to increase the strength of work timing to decrease the timing error generated from the work timing drift. However, if the strength of work timing is set larger than needed in the design stage, circuit area and design would be wasted.